The present invention relates to a power bus grid architecture for integrated circuits, and in particular, the present invention relates to a power bus grid architecture that is adapted for the amount of current to be carried therethrough.
A great number of modem electronic circuits are located in integrated circuits (ICs). ICs feature circuits whose components and conductors connecting the components are made by processing distinct areas of a chip of semi-conductor material, such as silicon. The connections between the thousands of circuits include signal lines and power distribution lines that supply voltage and ground potentials to the individual circuits.
One type of IC is known as an Application Specific Integrated Circuit (ASIC). Many complex ASICs include a standard power bus architecture which is often in the form of a grid, with a plurality of power bus bars arranged in an orthogonal fashion.
In ICs, there are at least two important design criteria for the power bus bars. One is the permissible amount of voltage drop at various points in the power bus grid. The voltage drop along a conductor of a given length is a function of the current flowing through the conductor and the electrical resistance of the conductor. The electrical resistance of a length of conductor is a function of the resistivity of the material that the conductor is composed of, the length of the conductor, and the cross-sectional area of the conductor. Thus, the narrower the cross-sectional of a conductor, for a given length, the higher the resistance will be of the conductor. Accordingly, the voltage drop across one length of conductor is equal to the current flowing therethrough times the resistance. Power bus grid architectures are typically designed with bus bars of a sufficiently-large cross-sectional area throughout so that the voltage drop at the worst case position on the IC (typically the center of the IC) is at an acceptable level.
Another important design criteria for power bus grid architectures in ICs is related to the reliability and/or nominal lifetime of the bus bars and the power bus grid architecture. One primary driver in the reliability/lifetime of an IC is an effect known as electromigration. The electromigration effect causes a gradual deterioration of any conductor as a function of the current density therethrough. Electromigration is the movement of atoms in the conductor caused by the interaction between electrons and ions in the conductor under the presence of electrical currents. In other words, as current flows through a conductor, the atoms of the conductor are gradually depleted. With small conductors, significant current densities, and prolonged use, the conductor can eventually be deteriorated away to the point to where a failure in the related circuit is caused, either because of the complete lack of current flow through the conductor, or because of the greatly increased voltage drop through the conductor as a result of the effective cross-sectional area of the conductor being gradually diminished.
Again, as is the case with the voltage drop design criterion, it is typical for power bus grid architectures to be designed conservatively to withstand the predicted amount of electromigration in the bus bars over the desired lifetime of the IC. The necessary cross-sectional area and current density is considered for the worst case position in the power bus grid architecture (which position will vary depending upon the architecture). There are several drawbacks to this conservative design approach typically used in power bus grid architectures. The first is that the conservative approach provides an excessive amount of conductor material in the power bus grid architecture. This is not only a waste of material, but it makes the whole IC larger than would otherwise be necessary. Perhaps more importantly, it exacerbates a common problem in ICs of congestion in the center of the chip.
Of course, as integrated circuit size continues to decrease, these issues become more and more important. For this reason alone, it is important to provide a more optimal power bus grid architecture for ICs.
One prior art attempt to solve some of the above problems is disclosed in U.S. Pat. No. 5,311,058. This disclosure includes a power distribution system for an IC which includes a grid having at least one power bus and one ground bus attached to the top surface of the IC die. The grid is adapted to be electrically coupled with power and ground pins in the IC""s package. The grid has an insulated layer on its bottom surface to electrically isolate the grid""s bottom surface from the IC. The grid is adapted to cover substantially the entire top surface of the IC and to be electrically coupled by wires directly from the top surface of the grid to terminal or connection points on the top surface of the IC. The connection points can be distributed throughout the IC to reduce the area of metalization in the IC and the path length the current from the power buses must traverse. Unfortunately, this approach suffers from the drawbacks that bonding down to the IC from the grid may be very difficult. It may be difficult to bond wires directly to the integrated circuit without crushing or causing other damage to the circuit.
It is against this background, and the desire to solve the problems of and improve on the prior art, that the above invention has been developed.
One aspect of the present invention is directed to an integrated circuit which includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The power bus grid is formed of a plurality of power bus straps having a strap density that progressively varies with distance from the geometric center toward the periphery.
Another aspect of the present invention is directed to an integrated circuit which includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The grid is formed of a plurality of power bus straps, with a first set of the straps extending in a first direction and a second set of the straps extending in a second direction, perpendicular to the first direction, and wherein a density of the straps that intersect a straight line extending from the geometric center toward the periphery increases with increasing distance along the line.
Another aspect of the present invention is directed to an integrated circuit which includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid for providing electrical current to the plurality of circuits with increasing current density per unit area of the integrated circuit as the distance of each unit area from the geometric center increases.